/*
    Copyright (c) 2011 SMIC
    Filename:      S011HD1P_X32Y2D128_BW.v
    IP code :      S011HD1P
    Version:       0.1.a
    CreateDate:    Sep 17, 2021

    Verilog Model for Synchronous Single-Port Register File
    SMIC 0.11um General Logic Process

    Configuration: -instname S011HD1P_X32Y2D128_BW -rows 32 -bits 128 -mux 2 
    Redundancy: Off
    Bit-Write: On
*/

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`timescale 1ns/1ps
`celldefine

module S011HD1P_X32Y2D128_BW (
                          Q,
			  CLK,
			  CEN,
			  WEN,
                      BWEN,
			  A,
			  D);

  parameter	Bits = 128;
  parameter	Word_Depth = 64;
  parameter	Add_Width = 6;
  parameter     Wen_Width = 128;
  parameter     Word_Pt = 1;

  output [Bits-1:0]      	Q;
  input		   		CLK;
  input		   		CEN;
  input		   		WEN;
  input	[Wen_Width-1:0]         BWEN;
  input	[Add_Width-1:0] 	A;
  input	[Bits-1:0] 		D;


  wire [Bits-1:0] 	Q_int;
  wire [Add_Width-1:0] 	A_int;
  wire                 	CLK_int;
  wire                 	CEN_int;
  wire                 	WEN_int;
  wire [Wen_Width-1:0]  BWEN_int;
  wire [Bits-1:0] 	D_int;

  reg  [Bits-1:0] 	Q_latched;
  reg  [Add_Width-1:0] 	A_latched;
  reg  [Bits-1:0] 	D_latched;
  reg                  	CEN_latched;
  reg                   WEN_latched;
  reg                  	LAST_CLK;
  reg  [Wen_Width-1:0]      BWEN_latched;
  reg 			A0_flag;
  reg 			A1_flag;
  reg 			A2_flag;
  reg 			A3_flag;
  reg 			A4_flag;
  reg 			A5_flag;

  reg                	CEN_flag;
  reg                   WEN_flag;
  reg                   CLK_CYC_flag;
  reg                   CLK_H_flag;
  reg                   CLK_L_flag;

  reg 			D0_flag;
  reg 			D1_flag;
  reg 			D2_flag;
  reg 			D3_flag;
  reg 			D4_flag;
  reg 			D5_flag;
  reg 			D6_flag;
  reg 			D7_flag;
  reg 			D8_flag;
  reg 			D9_flag;
  reg 			D10_flag;
  reg 			D11_flag;
  reg 			D12_flag;
  reg 			D13_flag;
  reg 			D14_flag;
  reg 			D15_flag;
  reg 			D16_flag;
  reg 			D17_flag;
  reg 			D18_flag;
  reg 			D19_flag;
  reg 			D20_flag;
  reg 			D21_flag;
  reg 			D22_flag;
  reg 			D23_flag;
  reg 			D24_flag;
  reg 			D25_flag;
  reg 			D26_flag;
  reg 			D27_flag;
  reg 			D28_flag;
  reg 			D29_flag;
  reg 			D30_flag;
  reg 			D31_flag;
  reg 			D32_flag;
  reg 			D33_flag;
  reg 			D34_flag;
  reg 			D35_flag;
  reg 			D36_flag;
  reg 			D37_flag;
  reg 			D38_flag;
  reg 			D39_flag;
  reg 			D40_flag;
  reg 			D41_flag;
  reg 			D42_flag;
  reg 			D43_flag;
  reg 			D44_flag;
  reg 			D45_flag;
  reg 			D46_flag;
  reg 			D47_flag;
  reg 			D48_flag;
  reg 			D49_flag;
  reg 			D50_flag;
  reg 			D51_flag;
  reg 			D52_flag;
  reg 			D53_flag;
  reg 			D54_flag;
  reg 			D55_flag;
  reg 			D56_flag;
  reg 			D57_flag;
  reg 			D58_flag;
  reg 			D59_flag;
  reg 			D60_flag;
  reg 			D61_flag;
  reg 			D62_flag;
  reg 			D63_flag;
  reg 			D64_flag;
  reg 			D65_flag;
  reg 			D66_flag;
  reg 			D67_flag;
  reg 			D68_flag;
  reg 			D69_flag;
  reg 			D70_flag;
  reg 			D71_flag;
  reg 			D72_flag;
  reg 			D73_flag;
  reg 			D74_flag;
  reg 			D75_flag;
  reg 			D76_flag;
  reg 			D77_flag;
  reg 			D78_flag;
  reg 			D79_flag;
  reg 			D80_flag;
  reg 			D81_flag;
  reg 			D82_flag;
  reg 			D83_flag;
  reg 			D84_flag;
  reg 			D85_flag;
  reg 			D86_flag;
  reg 			D87_flag;
  reg 			D88_flag;
  reg 			D89_flag;
  reg 			D90_flag;
  reg 			D91_flag;
  reg 			D92_flag;
  reg 			D93_flag;
  reg 			D94_flag;
  reg 			D95_flag;
  reg 			D96_flag;
  reg 			D97_flag;
  reg 			D98_flag;
  reg 			D99_flag;
  reg 			D100_flag;
  reg 			D101_flag;
  reg 			D102_flag;
  reg 			D103_flag;
  reg 			D104_flag;
  reg 			D105_flag;
  reg 			D106_flag;
  reg 			D107_flag;
  reg 			D108_flag;
  reg 			D109_flag;
  reg 			D110_flag;
  reg 			D111_flag;
  reg 			D112_flag;
  reg 			D113_flag;
  reg 			D114_flag;
  reg 			D115_flag;
  reg 			D116_flag;
  reg 			D117_flag;
  reg 			D118_flag;
  reg 			D119_flag;
  reg 			D120_flag;
  reg 			D121_flag;
  reg 			D122_flag;
  reg 			D123_flag;
  reg 			D124_flag;
  reg 			D125_flag;
  reg 			D126_flag;
  reg 			D127_flag;
 reg 			BWEN0_flag;
 reg 			BWEN1_flag;
 reg 			BWEN2_flag;
 reg 			BWEN3_flag;
 reg 			BWEN4_flag;
 reg 			BWEN5_flag;
 reg 			BWEN6_flag;
 reg 			BWEN7_flag;
 reg 			BWEN8_flag;
 reg 			BWEN9_flag;
 reg 			BWEN10_flag;
 reg 			BWEN11_flag;
 reg 			BWEN12_flag;
 reg 			BWEN13_flag;
 reg 			BWEN14_flag;
 reg 			BWEN15_flag;
 reg 			BWEN16_flag;
 reg 			BWEN17_flag;
 reg 			BWEN18_flag;
 reg 			BWEN19_flag;
 reg 			BWEN20_flag;
 reg 			BWEN21_flag;
 reg 			BWEN22_flag;
 reg 			BWEN23_flag;
 reg 			BWEN24_flag;
 reg 			BWEN25_flag;
 reg 			BWEN26_flag;
 reg 			BWEN27_flag;
 reg 			BWEN28_flag;
 reg 			BWEN29_flag;
 reg 			BWEN30_flag;
 reg 			BWEN31_flag;
 reg 			BWEN32_flag;
 reg 			BWEN33_flag;
 reg 			BWEN34_flag;
 reg 			BWEN35_flag;
 reg 			BWEN36_flag;
 reg 			BWEN37_flag;
 reg 			BWEN38_flag;
 reg 			BWEN39_flag;
 reg 			BWEN40_flag;
 reg 			BWEN41_flag;
 reg 			BWEN42_flag;
 reg 			BWEN43_flag;
 reg 			BWEN44_flag;
 reg 			BWEN45_flag;
 reg 			BWEN46_flag;
 reg 			BWEN47_flag;
 reg 			BWEN48_flag;
 reg 			BWEN49_flag;
 reg 			BWEN50_flag;
 reg 			BWEN51_flag;
 reg 			BWEN52_flag;
 reg 			BWEN53_flag;
 reg 			BWEN54_flag;
 reg 			BWEN55_flag;
 reg 			BWEN56_flag;
 reg 			BWEN57_flag;
 reg 			BWEN58_flag;
 reg 			BWEN59_flag;
 reg 			BWEN60_flag;
 reg 			BWEN61_flag;
 reg 			BWEN62_flag;
 reg 			BWEN63_flag;
 reg 			BWEN64_flag;
 reg 			BWEN65_flag;
 reg 			BWEN66_flag;
 reg 			BWEN67_flag;
 reg 			BWEN68_flag;
 reg 			BWEN69_flag;
 reg 			BWEN70_flag;
 reg 			BWEN71_flag;
 reg 			BWEN72_flag;
 reg 			BWEN73_flag;
 reg 			BWEN74_flag;
 reg 			BWEN75_flag;
 reg 			BWEN76_flag;
 reg 			BWEN77_flag;
 reg 			BWEN78_flag;
 reg 			BWEN79_flag;
 reg 			BWEN80_flag;
 reg 			BWEN81_flag;
 reg 			BWEN82_flag;
 reg 			BWEN83_flag;
 reg 			BWEN84_flag;
 reg 			BWEN85_flag;
 reg 			BWEN86_flag;
 reg 			BWEN87_flag;
 reg 			BWEN88_flag;
 reg 			BWEN89_flag;
 reg 			BWEN90_flag;
 reg 			BWEN91_flag;
 reg 			BWEN92_flag;
 reg 			BWEN93_flag;
 reg 			BWEN94_flag;
 reg 			BWEN95_flag;
 reg 			BWEN96_flag;
 reg 			BWEN97_flag;
 reg 			BWEN98_flag;
 reg 			BWEN99_flag;
 reg 			BWEN100_flag;
 reg 			BWEN101_flag;
 reg 			BWEN102_flag;
 reg 			BWEN103_flag;
 reg 			BWEN104_flag;
 reg 			BWEN105_flag;
 reg 			BWEN106_flag;
 reg 			BWEN107_flag;
 reg 			BWEN108_flag;
 reg 			BWEN109_flag;
 reg 			BWEN110_flag;
 reg 			BWEN111_flag;
 reg 			BWEN112_flag;
 reg 			BWEN113_flag;
 reg 			BWEN114_flag;
 reg 			BWEN115_flag;
 reg 			BWEN116_flag;
 reg 			BWEN117_flag;
 reg 			BWEN118_flag;
 reg 			BWEN119_flag;
 reg 			BWEN120_flag;
 reg 			BWEN121_flag;
 reg 			BWEN122_flag;
 reg 			BWEN123_flag;
 reg 			BWEN124_flag;
 reg 			BWEN125_flag;
 reg 			BWEN126_flag;
 reg 			BWEN127_flag;


  reg [Wen_Width-1:0]     BWEN_flag;
  reg [Add_Width-1:0]   A_flag;
  reg [Bits-1:0]        D_flag;
  reg                   LAST_CEN_flag;
  reg                   LAST_WEN_flag;
  reg [Wen_Width-1:0]   LAST_BWEN_flag;
  reg [Add_Width-1:0]   LAST_A_flag;
  reg [Bits-1:0]        LAST_D_flag;

  reg                   LAST_CLK_CYC_flag;
  reg                   LAST_CLK_H_flag;
  reg                   LAST_CLK_L_flag;

  reg [Bits-1:0]          data_tmp;

  wire                  CE_flag;
  wire                  WR0_flag;
  wire                  WR1_flag;
  wire                  WR2_flag;
  wire                  WR3_flag;
  wire                  WR4_flag;
  wire                  WR5_flag;
  wire                  WR6_flag;
  wire                  WR7_flag;
  wire                  WR8_flag;
  wire                  WR9_flag;
  wire                  WR10_flag;
  wire                  WR11_flag;
  wire                  WR12_flag;
  wire                  WR13_flag;
  wire                  WR14_flag;
  wire                  WR15_flag;
  wire                  WR16_flag;
  wire                  WR17_flag;
  wire                  WR18_flag;
  wire                  WR19_flag;
  wire                  WR20_flag;
  wire                  WR21_flag;
  wire                  WR22_flag;
  wire                  WR23_flag;
  wire                  WR24_flag;
  wire                  WR25_flag;
  wire                  WR26_flag;
  wire                  WR27_flag;
  wire                  WR28_flag;
  wire                  WR29_flag;
  wire                  WR30_flag;
  wire                  WR31_flag;
  wire                  WR32_flag;
  wire                  WR33_flag;
  wire                  WR34_flag;
  wire                  WR35_flag;
  wire                  WR36_flag;
  wire                  WR37_flag;
  wire                  WR38_flag;
  wire                  WR39_flag;
  wire                  WR40_flag;
  wire                  WR41_flag;
  wire                  WR42_flag;
  wire                  WR43_flag;
  wire                  WR44_flag;
  wire                  WR45_flag;
  wire                  WR46_flag;
  wire                  WR47_flag;
  wire                  WR48_flag;
  wire                  WR49_flag;
  wire                  WR50_flag;
  wire                  WR51_flag;
  wire                  WR52_flag;
  wire                  WR53_flag;
  wire                  WR54_flag;
  wire                  WR55_flag;
  wire                  WR56_flag;
  wire                  WR57_flag;
  wire                  WR58_flag;
  wire                  WR59_flag;
  wire                  WR60_flag;
  wire                  WR61_flag;
  wire                  WR62_flag;
  wire                  WR63_flag;
  wire                  WR64_flag;
  wire                  WR65_flag;
  wire                  WR66_flag;
  wire                  WR67_flag;
  wire                  WR68_flag;
  wire                  WR69_flag;
  wire                  WR70_flag;
  wire                  WR71_flag;
  wire                  WR72_flag;
  wire                  WR73_flag;
  wire                  WR74_flag;
  wire                  WR75_flag;
  wire                  WR76_flag;
  wire                  WR77_flag;
  wire                  WR78_flag;
  wire                  WR79_flag;
  wire                  WR80_flag;
  wire                  WR81_flag;
  wire                  WR82_flag;
  wire                  WR83_flag;
  wire                  WR84_flag;
  wire                  WR85_flag;
  wire                  WR86_flag;
  wire                  WR87_flag;
  wire                  WR88_flag;
  wire                  WR89_flag;
  wire                  WR90_flag;
  wire                  WR91_flag;
  wire                  WR92_flag;
  wire                  WR93_flag;
  wire                  WR94_flag;
  wire                  WR95_flag;
  wire                  WR96_flag;
  wire                  WR97_flag;
  wire                  WR98_flag;
  wire                  WR99_flag;
  wire                  WR100_flag;
  wire                  WR101_flag;
  wire                  WR102_flag;
  wire                  WR103_flag;
  wire                  WR104_flag;
  wire                  WR105_flag;
  wire                  WR106_flag;
  wire                  WR107_flag;
  wire                  WR108_flag;
  wire                  WR109_flag;
  wire                  WR110_flag;
  wire                  WR111_flag;
  wire                  WR112_flag;
  wire                  WR113_flag;
  wire                  WR114_flag;
  wire                  WR115_flag;
  wire                  WR116_flag;
  wire                  WR117_flag;
  wire                  WR118_flag;
  wire                  WR119_flag;
  wire                  WR120_flag;
  wire                  WR121_flag;
  wire                  WR122_flag;
  wire                  WR123_flag;
  wire                  WR124_flag;
  wire                  WR125_flag;
  wire                  WR126_flag;
  wire                  WR127_flag;
  reg    [Bits-1:0] 	mem_array[Word_Depth-1:0];

  integer      i,j,wenn,lb,hb;
  integer      n;

  buf dout_buf[Bits-1:0] (Q, Q_int);
  buf (CLK_int, CLK);
  buf (CEN_int, CEN);
  buf (WEN_int, WEN);
  buf wen_buf[Wen_Width-1:0] (BWEN_int, BWEN);
  buf a_buf[Add_Width-1:0] (A_int, A);
  buf din_buf[Bits-1:0] (D_int, D);   

  assign Q_int=Q_latched;
  assign CE_flag=!CEN_int;
  assign WR0_flag=(!CEN_int && !WEN_int && !BWEN_int[0]);
  assign WR1_flag=(!CEN_int && !WEN_int && !BWEN_int[1]);
  assign WR2_flag=(!CEN_int && !WEN_int && !BWEN_int[2]);
  assign WR3_flag=(!CEN_int && !WEN_int && !BWEN_int[3]);
  assign WR4_flag=(!CEN_int && !WEN_int && !BWEN_int[4]);
  assign WR5_flag=(!CEN_int && !WEN_int && !BWEN_int[5]);
  assign WR6_flag=(!CEN_int && !WEN_int && !BWEN_int[6]);
  assign WR7_flag=(!CEN_int && !WEN_int && !BWEN_int[7]);
  assign WR8_flag=(!CEN_int && !WEN_int && !BWEN_int[8]);
  assign WR9_flag=(!CEN_int && !WEN_int && !BWEN_int[9]);
  assign WR10_flag=(!CEN_int && !WEN_int && !BWEN_int[10]);
  assign WR11_flag=(!CEN_int && !WEN_int && !BWEN_int[11]);
  assign WR12_flag=(!CEN_int && !WEN_int && !BWEN_int[12]);
  assign WR13_flag=(!CEN_int && !WEN_int && !BWEN_int[13]);
  assign WR14_flag=(!CEN_int && !WEN_int && !BWEN_int[14]);
  assign WR15_flag=(!CEN_int && !WEN_int && !BWEN_int[15]);
  assign WR16_flag=(!CEN_int && !WEN_int && !BWEN_int[16]);
  assign WR17_flag=(!CEN_int && !WEN_int && !BWEN_int[17]);
  assign WR18_flag=(!CEN_int && !WEN_int && !BWEN_int[18]);
  assign WR19_flag=(!CEN_int && !WEN_int && !BWEN_int[19]);
  assign WR20_flag=(!CEN_int && !WEN_int && !BWEN_int[20]);
  assign WR21_flag=(!CEN_int && !WEN_int && !BWEN_int[21]);
  assign WR22_flag=(!CEN_int && !WEN_int && !BWEN_int[22]);
  assign WR23_flag=(!CEN_int && !WEN_int && !BWEN_int[23]);
  assign WR24_flag=(!CEN_int && !WEN_int && !BWEN_int[24]);
  assign WR25_flag=(!CEN_int && !WEN_int && !BWEN_int[25]);
  assign WR26_flag=(!CEN_int && !WEN_int && !BWEN_int[26]);
  assign WR27_flag=(!CEN_int && !WEN_int && !BWEN_int[27]);
  assign WR28_flag=(!CEN_int && !WEN_int && !BWEN_int[28]);
  assign WR29_flag=(!CEN_int && !WEN_int && !BWEN_int[29]);
  assign WR30_flag=(!CEN_int && !WEN_int && !BWEN_int[30]);
  assign WR31_flag=(!CEN_int && !WEN_int && !BWEN_int[31]);
  assign WR32_flag=(!CEN_int && !WEN_int && !BWEN_int[32]);
  assign WR33_flag=(!CEN_int && !WEN_int && !BWEN_int[33]);
  assign WR34_flag=(!CEN_int && !WEN_int && !BWEN_int[34]);
  assign WR35_flag=(!CEN_int && !WEN_int && !BWEN_int[35]);
  assign WR36_flag=(!CEN_int && !WEN_int && !BWEN_int[36]);
  assign WR37_flag=(!CEN_int && !WEN_int && !BWEN_int[37]);
  assign WR38_flag=(!CEN_int && !WEN_int && !BWEN_int[38]);
  assign WR39_flag=(!CEN_int && !WEN_int && !BWEN_int[39]);
  assign WR40_flag=(!CEN_int && !WEN_int && !BWEN_int[40]);
  assign WR41_flag=(!CEN_int && !WEN_int && !BWEN_int[41]);
  assign WR42_flag=(!CEN_int && !WEN_int && !BWEN_int[42]);
  assign WR43_flag=(!CEN_int && !WEN_int && !BWEN_int[43]);
  assign WR44_flag=(!CEN_int && !WEN_int && !BWEN_int[44]);
  assign WR45_flag=(!CEN_int && !WEN_int && !BWEN_int[45]);
  assign WR46_flag=(!CEN_int && !WEN_int && !BWEN_int[46]);
  assign WR47_flag=(!CEN_int && !WEN_int && !BWEN_int[47]);
  assign WR48_flag=(!CEN_int && !WEN_int && !BWEN_int[48]);
  assign WR49_flag=(!CEN_int && !WEN_int && !BWEN_int[49]);
  assign WR50_flag=(!CEN_int && !WEN_int && !BWEN_int[50]);
  assign WR51_flag=(!CEN_int && !WEN_int && !BWEN_int[51]);
  assign WR52_flag=(!CEN_int && !WEN_int && !BWEN_int[52]);
  assign WR53_flag=(!CEN_int && !WEN_int && !BWEN_int[53]);
  assign WR54_flag=(!CEN_int && !WEN_int && !BWEN_int[54]);
  assign WR55_flag=(!CEN_int && !WEN_int && !BWEN_int[55]);
  assign WR56_flag=(!CEN_int && !WEN_int && !BWEN_int[56]);
  assign WR57_flag=(!CEN_int && !WEN_int && !BWEN_int[57]);
  assign WR58_flag=(!CEN_int && !WEN_int && !BWEN_int[58]);
  assign WR59_flag=(!CEN_int && !WEN_int && !BWEN_int[59]);
  assign WR60_flag=(!CEN_int && !WEN_int && !BWEN_int[60]);
  assign WR61_flag=(!CEN_int && !WEN_int && !BWEN_int[61]);
  assign WR62_flag=(!CEN_int && !WEN_int && !BWEN_int[62]);
  assign WR63_flag=(!CEN_int && !WEN_int && !BWEN_int[63]);
  assign WR64_flag=(!CEN_int && !WEN_int && !BWEN_int[64]);
  assign WR65_flag=(!CEN_int && !WEN_int && !BWEN_int[65]);
  assign WR66_flag=(!CEN_int && !WEN_int && !BWEN_int[66]);
  assign WR67_flag=(!CEN_int && !WEN_int && !BWEN_int[67]);
  assign WR68_flag=(!CEN_int && !WEN_int && !BWEN_int[68]);
  assign WR69_flag=(!CEN_int && !WEN_int && !BWEN_int[69]);
  assign WR70_flag=(!CEN_int && !WEN_int && !BWEN_int[70]);
  assign WR71_flag=(!CEN_int && !WEN_int && !BWEN_int[71]);
  assign WR72_flag=(!CEN_int && !WEN_int && !BWEN_int[72]);
  assign WR73_flag=(!CEN_int && !WEN_int && !BWEN_int[73]);
  assign WR74_flag=(!CEN_int && !WEN_int && !BWEN_int[74]);
  assign WR75_flag=(!CEN_int && !WEN_int && !BWEN_int[75]);
  assign WR76_flag=(!CEN_int && !WEN_int && !BWEN_int[76]);
  assign WR77_flag=(!CEN_int && !WEN_int && !BWEN_int[77]);
  assign WR78_flag=(!CEN_int && !WEN_int && !BWEN_int[78]);
  assign WR79_flag=(!CEN_int && !WEN_int && !BWEN_int[79]);
  assign WR80_flag=(!CEN_int && !WEN_int && !BWEN_int[80]);
  assign WR81_flag=(!CEN_int && !WEN_int && !BWEN_int[81]);
  assign WR82_flag=(!CEN_int && !WEN_int && !BWEN_int[82]);
  assign WR83_flag=(!CEN_int && !WEN_int && !BWEN_int[83]);
  assign WR84_flag=(!CEN_int && !WEN_int && !BWEN_int[84]);
  assign WR85_flag=(!CEN_int && !WEN_int && !BWEN_int[85]);
  assign WR86_flag=(!CEN_int && !WEN_int && !BWEN_int[86]);
  assign WR87_flag=(!CEN_int && !WEN_int && !BWEN_int[87]);
  assign WR88_flag=(!CEN_int && !WEN_int && !BWEN_int[88]);
  assign WR89_flag=(!CEN_int && !WEN_int && !BWEN_int[89]);
  assign WR90_flag=(!CEN_int && !WEN_int && !BWEN_int[90]);
  assign WR91_flag=(!CEN_int && !WEN_int && !BWEN_int[91]);
  assign WR92_flag=(!CEN_int && !WEN_int && !BWEN_int[92]);
  assign WR93_flag=(!CEN_int && !WEN_int && !BWEN_int[93]);
  assign WR94_flag=(!CEN_int && !WEN_int && !BWEN_int[94]);
  assign WR95_flag=(!CEN_int && !WEN_int && !BWEN_int[95]);
  assign WR96_flag=(!CEN_int && !WEN_int && !BWEN_int[96]);
  assign WR97_flag=(!CEN_int && !WEN_int && !BWEN_int[97]);
  assign WR98_flag=(!CEN_int && !WEN_int && !BWEN_int[98]);
  assign WR99_flag=(!CEN_int && !WEN_int && !BWEN_int[99]);
  assign WR100_flag=(!CEN_int && !WEN_int && !BWEN_int[100]);
  assign WR101_flag=(!CEN_int && !WEN_int && !BWEN_int[101]);
  assign WR102_flag=(!CEN_int && !WEN_int && !BWEN_int[102]);
  assign WR103_flag=(!CEN_int && !WEN_int && !BWEN_int[103]);
  assign WR104_flag=(!CEN_int && !WEN_int && !BWEN_int[104]);
  assign WR105_flag=(!CEN_int && !WEN_int && !BWEN_int[105]);
  assign WR106_flag=(!CEN_int && !WEN_int && !BWEN_int[106]);
  assign WR107_flag=(!CEN_int && !WEN_int && !BWEN_int[107]);
  assign WR108_flag=(!CEN_int && !WEN_int && !BWEN_int[108]);
  assign WR109_flag=(!CEN_int && !WEN_int && !BWEN_int[109]);
  assign WR110_flag=(!CEN_int && !WEN_int && !BWEN_int[110]);
  assign WR111_flag=(!CEN_int && !WEN_int && !BWEN_int[111]);
  assign WR112_flag=(!CEN_int && !WEN_int && !BWEN_int[112]);
  assign WR113_flag=(!CEN_int && !WEN_int && !BWEN_int[113]);
  assign WR114_flag=(!CEN_int && !WEN_int && !BWEN_int[114]);
  assign WR115_flag=(!CEN_int && !WEN_int && !BWEN_int[115]);
  assign WR116_flag=(!CEN_int && !WEN_int && !BWEN_int[116]);
  assign WR117_flag=(!CEN_int && !WEN_int && !BWEN_int[117]);
  assign WR118_flag=(!CEN_int && !WEN_int && !BWEN_int[118]);
  assign WR119_flag=(!CEN_int && !WEN_int && !BWEN_int[119]);
  assign WR120_flag=(!CEN_int && !WEN_int && !BWEN_int[120]);
  assign WR121_flag=(!CEN_int && !WEN_int && !BWEN_int[121]);
  assign WR122_flag=(!CEN_int && !WEN_int && !BWEN_int[122]);
  assign WR123_flag=(!CEN_int && !WEN_int && !BWEN_int[123]);
  assign WR124_flag=(!CEN_int && !WEN_int && !BWEN_int[124]);
  assign WR125_flag=(!CEN_int && !WEN_int && !BWEN_int[125]);
  assign WR126_flag=(!CEN_int && !WEN_int && !BWEN_int[126]);
  assign WR127_flag=(!CEN_int && !WEN_int && !BWEN_int[127]);

  always @(CLK_int)
    begin
      casez({LAST_CLK, CLK_int})
        2'b01: begin
          CEN_latched = CEN_int;
          WEN_latched = WEN_int;
          BWEN_latched = BWEN_int;
          A_latched = A_int;
          D_latched = D_int;
          rw_mem;
        end
        2'b10,
        2'bx?,
        2'b00,
        2'b11: ;
        2'b?x: begin
	  for(i=0;i<Word_Depth;i=i+1)
    	    mem_array[i]={Bits{1'bx}};
    	  Q_latched={Bits{1'bx}};
          rw_mem;
          end
      endcase
    LAST_CLK=CLK_int;
   end

  always @(CEN_flag
           	or WEN_flag
		or BWEN0_flag
		or BWEN1_flag
		or BWEN2_flag
		or BWEN3_flag
		or BWEN4_flag
		or BWEN5_flag
		or BWEN6_flag
		or BWEN7_flag
		or BWEN8_flag
		or BWEN9_flag
		or BWEN10_flag
		or BWEN11_flag
		or BWEN12_flag
		or BWEN13_flag
		or BWEN14_flag
		or BWEN15_flag
		or BWEN16_flag
		or BWEN17_flag
		or BWEN18_flag
		or BWEN19_flag
		or BWEN20_flag
		or BWEN21_flag
		or BWEN22_flag
		or BWEN23_flag
		or BWEN24_flag
		or BWEN25_flag
		or BWEN26_flag
		or BWEN27_flag
		or BWEN28_flag
		or BWEN29_flag
		or BWEN30_flag
		or BWEN31_flag
		or BWEN32_flag
		or BWEN33_flag
		or BWEN34_flag
		or BWEN35_flag
		or BWEN36_flag
		or BWEN37_flag
		or BWEN38_flag
		or BWEN39_flag
		or BWEN40_flag
		or BWEN41_flag
		or BWEN42_flag
		or BWEN43_flag
		or BWEN44_flag
		or BWEN45_flag
		or BWEN46_flag
		or BWEN47_flag
		or BWEN48_flag
		or BWEN49_flag
		or BWEN50_flag
		or BWEN51_flag
		or BWEN52_flag
		or BWEN53_flag
		or BWEN54_flag
		or BWEN55_flag
		or BWEN56_flag
		or BWEN57_flag
		or BWEN58_flag
		or BWEN59_flag
		or BWEN60_flag
		or BWEN61_flag
		or BWEN62_flag
		or BWEN63_flag
		or BWEN64_flag
		or BWEN65_flag
		or BWEN66_flag
		or BWEN67_flag
		or BWEN68_flag
		or BWEN69_flag
		or BWEN70_flag
		or BWEN71_flag
		or BWEN72_flag
		or BWEN73_flag
		or BWEN74_flag
		or BWEN75_flag
		or BWEN76_flag
		or BWEN77_flag
		or BWEN78_flag
		or BWEN79_flag
		or BWEN80_flag
		or BWEN81_flag
		or BWEN82_flag
		or BWEN83_flag
		or BWEN84_flag
		or BWEN85_flag
		or BWEN86_flag
		or BWEN87_flag
		or BWEN88_flag
		or BWEN89_flag
		or BWEN90_flag
		or BWEN91_flag
		or BWEN92_flag
		or BWEN93_flag
		or BWEN94_flag
		or BWEN95_flag
		or BWEN96_flag
		or BWEN97_flag
		or BWEN98_flag
		or BWEN99_flag
		or BWEN100_flag
		or BWEN101_flag
		or BWEN102_flag
		or BWEN103_flag
		or BWEN104_flag
		or BWEN105_flag
		or BWEN106_flag
		or BWEN107_flag
		or BWEN108_flag
		or BWEN109_flag
		or BWEN110_flag
		or BWEN111_flag
		or BWEN112_flag
		or BWEN113_flag
		or BWEN114_flag
		or BWEN115_flag
		or BWEN116_flag
		or BWEN117_flag
		or BWEN118_flag
		or BWEN119_flag
		or BWEN120_flag
		or BWEN121_flag
		or BWEN122_flag
		or BWEN123_flag
		or BWEN124_flag
		or BWEN125_flag
		or BWEN126_flag
		or BWEN127_flag
		or A0_flag
		or A1_flag
		or A2_flag
		or A3_flag
		or A4_flag
		or A5_flag
		or D0_flag
		or D1_flag
		or D2_flag
		or D3_flag
		or D4_flag
		or D5_flag
		or D6_flag
		or D7_flag
		or D8_flag
		or D9_flag
		or D10_flag
		or D11_flag
		or D12_flag
		or D13_flag
		or D14_flag
		or D15_flag
		or D16_flag
		or D17_flag
		or D18_flag
		or D19_flag
		or D20_flag
		or D21_flag
		or D22_flag
		or D23_flag
		or D24_flag
		or D25_flag
		or D26_flag
		or D27_flag
		or D28_flag
		or D29_flag
		or D30_flag
		or D31_flag
		or D32_flag
		or D33_flag
		or D34_flag
		or D35_flag
		or D36_flag
		or D37_flag
		or D38_flag
		or D39_flag
		or D40_flag
		or D41_flag
		or D42_flag
		or D43_flag
		or D44_flag
		or D45_flag
		or D46_flag
		or D47_flag
		or D48_flag
		or D49_flag
		or D50_flag
		or D51_flag
		or D52_flag
		or D53_flag
		or D54_flag
		or D55_flag
		or D56_flag
		or D57_flag
		or D58_flag
		or D59_flag
		or D60_flag
		or D61_flag
		or D62_flag
		or D63_flag
		or D64_flag
		or D65_flag
		or D66_flag
		or D67_flag
		or D68_flag
		or D69_flag
		or D70_flag
		or D71_flag
		or D72_flag
		or D73_flag
		or D74_flag
		or D75_flag
		or D76_flag
		or D77_flag
		or D78_flag
		or D79_flag
		or D80_flag
		or D81_flag
		or D82_flag
		or D83_flag
		or D84_flag
		or D85_flag
		or D86_flag
		or D87_flag
		or D88_flag
		or D89_flag
		or D90_flag
		or D91_flag
		or D92_flag
		or D93_flag
		or D94_flag
		or D95_flag
		or D96_flag
		or D97_flag
		or D98_flag
		or D99_flag
		or D100_flag
		or D101_flag
		or D102_flag
		or D103_flag
		or D104_flag
		or D105_flag
		or D106_flag
		or D107_flag
		or D108_flag
		or D109_flag
		or D110_flag
		or D111_flag
		or D112_flag
		or D113_flag
		or D114_flag
		or D115_flag
		or D116_flag
		or D117_flag
		or D118_flag
		or D119_flag
		or D120_flag
		or D121_flag
		or D122_flag
		or D123_flag
		or D124_flag
		or D125_flag
		or D126_flag
		or D127_flag
           	or CLK_CYC_flag
           	or CLK_H_flag
           	or CLK_L_flag)
    begin
      update_flag_bus;
      CEN_latched = (CEN_flag!==LAST_CEN_flag) ? 1'bx : CEN_latched ;
      WEN_latched = (WEN_flag!==LAST_WEN_flag) ? 1'bx : WEN_latched ;
      for (n=0; n<Wen_Width; n=n+1)
      BWEN_latched[n] = (BWEN_flag[n]!==LAST_BWEN_flag[n]) ? 1'bx : BWEN_latched[n] ;
      for (n=0; n<Add_Width; n=n+1)
      A_latched[n] = (A_flag[n]!==LAST_A_flag[n]) ? 1'bx : A_latched[n] ;
      for (n=0; n<Bits; n=n+1)
      D_latched[n] = (D_flag[n]!==LAST_D_flag[n]) ? 1'bx : D_latched[n] ;
      LAST_CEN_flag = CEN_flag;
      LAST_WEN_flag = WEN_flag;
      LAST_BWEN_flag = BWEN_flag;
      LAST_A_flag = A_flag;
      LAST_D_flag = D_flag;
      LAST_CLK_CYC_flag = CLK_CYC_flag;
      LAST_CLK_H_flag = CLK_H_flag;
      LAST_CLK_L_flag = CLK_L_flag;
      rw_mem;
   end
      
   task rw_mem;
    begin
      if(CEN_latched==1'b0)
        begin
          if (WEN_latched==1'b1)
            begin
              if(^(A_latched)==1'bx)
                Q_latched={Bits{1'bx}};
              else
                Q_latched=mem_array[A_latched];
            end
          else if (WEN_latched==1'b0)
          begin
            for (wenn=0; wenn<Wen_Width; wenn=wenn+1)
              begin
                lb=wenn*Word_Pt;
                if ( (lb+Word_Pt) >= Bits) hb=Bits-1;
                else hb=lb+Word_Pt-1;
                if (BWEN_latched[wenn]==1'b1)
                  begin
                    if(^(A_latched)==1'bx)
                      for (i=lb; i<=hb; i=i+1) Q_latched[i]=1'bx;
                    else
                      begin
                      data_tmp=mem_array[A_latched];
                      for (i=lb; i<=hb; i=i+1) Q_latched[i]=data_tmp[i];
                      end
                  end
                else if (BWEN_latched[wenn]==1'b0)
                  begin
                    if (^(A_latched)==1'bx)
                      begin
                        for (i=0; i<Word_Depth; i=i+1)
                          begin
                            data_tmp=mem_array[i];
                            for (j=lb; j<=hb; j=j+1) data_tmp[j]=1'bx;
                            mem_array[i]=data_tmp;
                          end
                        for (i=lb; i<=hb; i=i+1) Q_latched[i]=1'bx;
                      end
                    else
                      begin
                        data_tmp=mem_array[A_latched];
                        for (i=lb; i<=hb; i=i+1) data_tmp[i]=D_latched[i];
                        mem_array[A_latched]=data_tmp;
                        for (i=lb; i<=hb; i=i+1) Q_latched[i]=data_tmp[i];
                      end
                  end
                else
                  begin
                    for (i=lb; i<=hb;i=i+1) Q_latched[i]=1'bx;
                    if (^(A_latched)==1'bx)
                      begin
                        for (i=0; i<Word_Depth; i=i+1)
                          begin
                            data_tmp=mem_array[i];
                            for (j=lb; j<=hb; j=j+1) data_tmp[j]=1'bx;
                            mem_array[i]=data_tmp;
                          end
                      end
                    else
                      begin
                        data_tmp=mem_array[A_latched];
                        for (i=lb; i<=hb; i=i+1) data_tmp[i]=1'bx;
                        mem_array[A_latched]=data_tmp;
                      end
                 end
               end
             end
           else
             begin
               for (wenn=0; wenn<Wen_Width; wenn=wenn+1)
               begin
                 lb=wenn*Word_Pt;
                 if ( (lb+Word_Pt) >= Bits) hb=Bits-1;
                 else hb=lb+Word_Pt-1;
                 if (BWEN_latched[wenn]==1'b1)
                  begin
                    if(^(A_latched)==1'bx)
                      for (i=lb; i<=hb; i=i+1) Q_latched[i]=1'bx;
                    else
                      begin
                      data_tmp=mem_array[A_latched];
                      for (i=lb; i<=hb; i=i+1) Q_latched[i]=data_tmp[i];
                      end
                  end
                else
                  begin
                    for (i=lb; i<=hb;i=i+1) Q_latched[i]=1'bx;
                    if (^(A_latched)==1'bx)
                      begin
                        for (i=0; i<Word_Depth; i=i+1)
                          begin
                            data_tmp=mem_array[i];
                            for (j=lb; j<=hb; j=j+1) data_tmp[j]=1'bx;
                            mem_array[i]=data_tmp;
                          end
                      end
                    else
                      begin
                        data_tmp=mem_array[A_latched];
                        for (i=lb; i<=hb; i=i+1) data_tmp[i]=1'bx;
                        mem_array[A_latched]=data_tmp;
                      end
                 end
               end
             end
           end
         else if (CEN_latched==1'bx)
           begin
             for (wenn=0;wenn<Wen_Width;wenn=wenn+1)
            begin
              lb=wenn*Word_Pt;
              if ((lb+Word_Pt)>=Bits) hb=Bits-1;
              else hb=lb+Word_Pt-1;
              if(WEN_latched==1'b1 || BWEN_latched[wenn]==1'b1)
                for (i=lb;i<=hb;i=i+1) Q_latched[i]=1'bx;
              else
                begin
                  for (i=lb;i<=hb;i=i+1) Q_latched[i]=1'bx;
                  if(^(A_latched)==1'bx)
                    begin
                      for (i=0;i<Word_Depth;i=i+1)
                        begin
                          data_tmp=mem_array[i];
                          for (j=lb;j<=hb;j=j+1) data_tmp[j]=1'bx;
                          mem_array[i]=data_tmp;
                        end
                    end
                  else
                    begin
                      data_tmp=mem_array[A_latched];
                      for (i=lb;i<=hb;i=i+1) data_tmp[i]=1'bx;
                      mem_array[A_latched]=data_tmp;
                    end
                end
            end
        end
    end
  endtask
     
   task x_mem;
   begin
     for(i=0;i<Word_Depth;i=i+1)
     mem_array[i]={Bits{1'bx}};
   end
   endtask

  task update_flag_bus;
  begin
 BWEN_flag = {

	    BWEN127_flag,
	    BWEN126_flag,
	    BWEN125_flag,
	    BWEN124_flag,
	    BWEN123_flag,
	    BWEN122_flag,
	    BWEN121_flag,
	    BWEN120_flag,
	    BWEN119_flag,
	    BWEN118_flag,
	    BWEN117_flag,
	    BWEN116_flag,
	    BWEN115_flag,
	    BWEN114_flag,
	    BWEN113_flag,
	    BWEN112_flag,
	    BWEN111_flag,
	    BWEN110_flag,
	    BWEN109_flag,
	    BWEN108_flag,
	    BWEN107_flag,
	    BWEN106_flag,
	    BWEN105_flag,
	    BWEN104_flag,
	    BWEN103_flag,
	    BWEN102_flag,
	    BWEN101_flag,
	    BWEN100_flag,
	    BWEN99_flag,
	    BWEN98_flag,
	    BWEN97_flag,
	    BWEN96_flag,
	    BWEN95_flag,
	    BWEN94_flag,
	    BWEN93_flag,
	    BWEN92_flag,
	    BWEN91_flag,
	    BWEN90_flag,
	    BWEN89_flag,
	    BWEN88_flag,
	    BWEN87_flag,
	    BWEN86_flag,
	    BWEN85_flag,
	    BWEN84_flag,
	    BWEN83_flag,
	    BWEN82_flag,
	    BWEN81_flag,
	    BWEN80_flag,
	    BWEN79_flag,
	    BWEN78_flag,
	    BWEN77_flag,
	    BWEN76_flag,
	    BWEN75_flag,
	    BWEN74_flag,
	    BWEN73_flag,
	    BWEN72_flag,
	    BWEN71_flag,
	    BWEN70_flag,
	    BWEN69_flag,
	    BWEN68_flag,
	    BWEN67_flag,
	    BWEN66_flag,
	    BWEN65_flag,
	    BWEN64_flag,
	    BWEN63_flag,
	    BWEN62_flag,
	    BWEN61_flag,
	    BWEN60_flag,
	    BWEN59_flag,
	    BWEN58_flag,
	    BWEN57_flag,
	    BWEN56_flag,
	    BWEN55_flag,
	    BWEN54_flag,
	    BWEN53_flag,
	    BWEN52_flag,
	    BWEN51_flag,
	    BWEN50_flag,
	    BWEN49_flag,
	    BWEN48_flag,
	    BWEN47_flag,
	    BWEN46_flag,
	    BWEN45_flag,
	    BWEN44_flag,
	    BWEN43_flag,
	    BWEN42_flag,
	    BWEN41_flag,
	    BWEN40_flag,
	    BWEN39_flag,
	    BWEN38_flag,
	    BWEN37_flag,
	    BWEN36_flag,
	    BWEN35_flag,
	    BWEN34_flag,
	    BWEN33_flag,
	    BWEN32_flag,
	    BWEN31_flag,
	    BWEN30_flag,
	    BWEN29_flag,
	    BWEN28_flag,
	    BWEN27_flag,
	    BWEN26_flag,
	    BWEN25_flag,
	    BWEN24_flag,
	    BWEN23_flag,
	    BWEN22_flag,
	    BWEN21_flag,
	    BWEN20_flag,
	    BWEN19_flag,
	    BWEN18_flag,
	    BWEN17_flag,
	    BWEN16_flag,
	    BWEN15_flag,
	    BWEN14_flag,
	    BWEN13_flag,
	    BWEN12_flag,
	    BWEN11_flag,
	    BWEN10_flag,
	    BWEN9_flag,
	    BWEN8_flag,
	    BWEN7_flag,
	    BWEN6_flag,
	    BWEN5_flag,
	    BWEN4_flag,
	    BWEN3_flag,
	    BWEN2_flag,
	    BWEN1_flag,
            BWEN0_flag};
    A_flag = {
		A5_flag,
		A4_flag,
		A3_flag,
		A2_flag,
		A1_flag,
            A0_flag};
    D_flag = {
		D127_flag,
		D126_flag,
		D125_flag,
		D124_flag,
		D123_flag,
		D122_flag,
		D121_flag,
		D120_flag,
		D119_flag,
		D118_flag,
		D117_flag,
		D116_flag,
		D115_flag,
		D114_flag,
		D113_flag,
		D112_flag,
		D111_flag,
		D110_flag,
		D109_flag,
		D108_flag,
		D107_flag,
		D106_flag,
		D105_flag,
		D104_flag,
		D103_flag,
		D102_flag,
		D101_flag,
		D100_flag,
		D99_flag,
		D98_flag,
		D97_flag,
		D96_flag,
		D95_flag,
		D94_flag,
		D93_flag,
		D92_flag,
		D91_flag,
		D90_flag,
		D89_flag,
		D88_flag,
		D87_flag,
		D86_flag,
		D85_flag,
		D84_flag,
		D83_flag,
		D82_flag,
		D81_flag,
		D80_flag,
		D79_flag,
		D78_flag,
		D77_flag,
		D76_flag,
		D75_flag,
		D74_flag,
		D73_flag,
		D72_flag,
		D71_flag,
		D70_flag,
		D69_flag,
		D68_flag,
		D67_flag,
		D66_flag,
		D65_flag,
		D64_flag,
		D63_flag,
		D62_flag,
		D61_flag,
		D60_flag,
		D59_flag,
		D58_flag,
		D57_flag,
		D56_flag,
		D55_flag,
		D54_flag,
		D53_flag,
		D52_flag,
		D51_flag,
		D50_flag,
		D49_flag,
		D48_flag,
		D47_flag,
		D46_flag,
		D45_flag,
		D44_flag,
		D43_flag,
		D42_flag,
		D41_flag,
		D40_flag,
		D39_flag,
		D38_flag,
		D37_flag,
		D36_flag,
		D35_flag,
		D34_flag,
		D33_flag,
		D32_flag,
		D31_flag,
		D30_flag,
		D29_flag,
		D28_flag,
		D27_flag,
		D26_flag,
		D25_flag,
		D24_flag,
		D23_flag,
		D22_flag,
		D21_flag,
		D20_flag,
		D19_flag,
		D18_flag,
		D17_flag,
		D16_flag,
		D15_flag,
		D14_flag,
		D13_flag,
		D12_flag,
		D11_flag,
		D10_flag,
		D9_flag,
		D8_flag,
		D7_flag,
		D6_flag,
		D5_flag,
		D4_flag,
		D3_flag,
		D2_flag,
		D1_flag,
            D0_flag};
   end
   endtask

  specify
    (posedge CLK => (Q[0] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[1] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[2] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[3] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[4] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[5] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[6] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[7] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[8] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[9] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[10] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[11] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[12] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[13] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[14] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[15] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[16] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[17] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[18] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[19] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[20] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[21] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[22] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[23] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[24] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[25] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[26] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[27] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[28] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[29] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[30] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[31] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[32] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[33] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[34] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[35] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[36] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[37] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[38] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[39] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[40] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[41] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[42] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[43] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[44] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[45] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[46] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[47] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[48] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[49] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[50] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[51] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[52] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[53] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[54] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[55] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[56] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[57] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[58] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[59] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[60] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[61] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[62] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[63] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[64] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[65] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[66] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[67] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[68] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[69] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[70] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[71] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[72] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[73] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[74] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[75] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[76] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[77] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[78] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[79] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[80] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[81] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[82] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[83] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[84] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[85] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[86] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[87] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[88] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[89] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[90] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[91] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[92] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[93] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[94] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[95] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[96] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[97] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[98] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[99] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[100] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[101] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[102] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[103] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[104] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[105] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[106] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[107] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[108] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[109] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[110] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[111] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[112] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[113] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[114] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[115] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[116] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[117] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[118] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[119] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[120] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[121] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[122] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[123] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[124] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[125] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[126] : 1'bx))=(1.000,1.000);
    (posedge CLK => (Q[127] : 1'bx))=(1.000,1.000);
    $setuphold(posedge CLK &&& CE_flag,posedge A[0],0.500,0.250,A0_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[0],0.500,0.250,A0_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge A[1],0.500,0.250,A1_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[1],0.500,0.250,A1_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge A[2],0.500,0.250,A2_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[2],0.500,0.250,A2_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge A[3],0.500,0.250,A3_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[3],0.500,0.250,A3_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge A[4],0.500,0.250,A4_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[4],0.500,0.250,A4_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge A[5],0.500,0.250,A5_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge A[5],0.500,0.250,A5_flag);
    $setuphold(posedge CLK,posedge CEN,0.500,0.250,CEN_flag);
    $setuphold(posedge CLK,negedge CEN,0.500,0.250,CEN_flag);
    $setuphold(posedge CLK,posedge WEN,0.500,0.250,WEN_flag);
    $setuphold(posedge CLK,negedge WEN,0.500,0.250,WEN_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[0],0.500,0.250,BWEN0_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[0],0.500,0.250,BWEN0_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[1],0.500,0.250,BWEN1_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[1],0.500,0.250,BWEN1_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[2],0.500,0.250,BWEN2_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[2],0.500,0.250,BWEN2_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[3],0.500,0.250,BWEN3_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[3],0.500,0.250,BWEN3_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[4],0.500,0.250,BWEN4_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[4],0.500,0.250,BWEN4_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[5],0.500,0.250,BWEN5_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[5],0.500,0.250,BWEN5_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[6],0.500,0.250,BWEN6_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[6],0.500,0.250,BWEN6_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[7],0.500,0.250,BWEN7_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[7],0.500,0.250,BWEN7_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[8],0.500,0.250,BWEN8_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[8],0.500,0.250,BWEN8_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[9],0.500,0.250,BWEN9_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[9],0.500,0.250,BWEN9_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[10],0.500,0.250,BWEN10_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[10],0.500,0.250,BWEN10_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[11],0.500,0.250,BWEN11_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[11],0.500,0.250,BWEN11_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[12],0.500,0.250,BWEN12_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[12],0.500,0.250,BWEN12_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[13],0.500,0.250,BWEN13_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[13],0.500,0.250,BWEN13_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[14],0.500,0.250,BWEN14_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[14],0.500,0.250,BWEN14_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[15],0.500,0.250,BWEN15_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[15],0.500,0.250,BWEN15_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[16],0.500,0.250,BWEN16_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[16],0.500,0.250,BWEN16_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[17],0.500,0.250,BWEN17_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[17],0.500,0.250,BWEN17_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[18],0.500,0.250,BWEN18_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[18],0.500,0.250,BWEN18_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[19],0.500,0.250,BWEN19_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[19],0.500,0.250,BWEN19_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[20],0.500,0.250,BWEN20_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[20],0.500,0.250,BWEN20_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[21],0.500,0.250,BWEN21_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[21],0.500,0.250,BWEN21_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[22],0.500,0.250,BWEN22_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[22],0.500,0.250,BWEN22_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[23],0.500,0.250,BWEN23_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[23],0.500,0.250,BWEN23_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[24],0.500,0.250,BWEN24_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[24],0.500,0.250,BWEN24_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[25],0.500,0.250,BWEN25_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[25],0.500,0.250,BWEN25_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[26],0.500,0.250,BWEN26_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[26],0.500,0.250,BWEN26_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[27],0.500,0.250,BWEN27_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[27],0.500,0.250,BWEN27_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[28],0.500,0.250,BWEN28_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[28],0.500,0.250,BWEN28_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[29],0.500,0.250,BWEN29_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[29],0.500,0.250,BWEN29_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[30],0.500,0.250,BWEN30_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[30],0.500,0.250,BWEN30_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[31],0.500,0.250,BWEN31_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[31],0.500,0.250,BWEN31_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[32],0.500,0.250,BWEN32_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[32],0.500,0.250,BWEN32_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[33],0.500,0.250,BWEN33_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[33],0.500,0.250,BWEN33_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[34],0.500,0.250,BWEN34_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[34],0.500,0.250,BWEN34_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[35],0.500,0.250,BWEN35_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[35],0.500,0.250,BWEN35_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[36],0.500,0.250,BWEN36_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[36],0.500,0.250,BWEN36_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[37],0.500,0.250,BWEN37_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[37],0.500,0.250,BWEN37_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[38],0.500,0.250,BWEN38_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[38],0.500,0.250,BWEN38_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[39],0.500,0.250,BWEN39_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[39],0.500,0.250,BWEN39_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[40],0.500,0.250,BWEN40_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[40],0.500,0.250,BWEN40_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[41],0.500,0.250,BWEN41_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[41],0.500,0.250,BWEN41_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[42],0.500,0.250,BWEN42_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[42],0.500,0.250,BWEN42_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[43],0.500,0.250,BWEN43_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[43],0.500,0.250,BWEN43_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[44],0.500,0.250,BWEN44_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[44],0.500,0.250,BWEN44_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[45],0.500,0.250,BWEN45_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[45],0.500,0.250,BWEN45_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[46],0.500,0.250,BWEN46_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[46],0.500,0.250,BWEN46_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[47],0.500,0.250,BWEN47_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[47],0.500,0.250,BWEN47_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[48],0.500,0.250,BWEN48_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[48],0.500,0.250,BWEN48_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[49],0.500,0.250,BWEN49_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[49],0.500,0.250,BWEN49_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[50],0.500,0.250,BWEN50_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[50],0.500,0.250,BWEN50_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[51],0.500,0.250,BWEN51_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[51],0.500,0.250,BWEN51_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[52],0.500,0.250,BWEN52_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[52],0.500,0.250,BWEN52_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[53],0.500,0.250,BWEN53_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[53],0.500,0.250,BWEN53_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[54],0.500,0.250,BWEN54_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[54],0.500,0.250,BWEN54_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[55],0.500,0.250,BWEN55_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[55],0.500,0.250,BWEN55_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[56],0.500,0.250,BWEN56_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[56],0.500,0.250,BWEN56_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[57],0.500,0.250,BWEN57_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[57],0.500,0.250,BWEN57_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[58],0.500,0.250,BWEN58_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[58],0.500,0.250,BWEN58_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[59],0.500,0.250,BWEN59_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[59],0.500,0.250,BWEN59_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[60],0.500,0.250,BWEN60_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[60],0.500,0.250,BWEN60_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[61],0.500,0.250,BWEN61_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[61],0.500,0.250,BWEN61_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[62],0.500,0.250,BWEN62_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[62],0.500,0.250,BWEN62_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[63],0.500,0.250,BWEN63_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[63],0.500,0.250,BWEN63_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[64],0.500,0.250,BWEN64_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[64],0.500,0.250,BWEN64_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[65],0.500,0.250,BWEN65_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[65],0.500,0.250,BWEN65_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[66],0.500,0.250,BWEN66_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[66],0.500,0.250,BWEN66_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[67],0.500,0.250,BWEN67_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[67],0.500,0.250,BWEN67_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[68],0.500,0.250,BWEN68_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[68],0.500,0.250,BWEN68_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[69],0.500,0.250,BWEN69_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[69],0.500,0.250,BWEN69_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[70],0.500,0.250,BWEN70_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[70],0.500,0.250,BWEN70_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[71],0.500,0.250,BWEN71_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[71],0.500,0.250,BWEN71_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[72],0.500,0.250,BWEN72_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[72],0.500,0.250,BWEN72_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[73],0.500,0.250,BWEN73_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[73],0.500,0.250,BWEN73_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[74],0.500,0.250,BWEN74_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[74],0.500,0.250,BWEN74_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[75],0.500,0.250,BWEN75_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[75],0.500,0.250,BWEN75_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[76],0.500,0.250,BWEN76_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[76],0.500,0.250,BWEN76_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[77],0.500,0.250,BWEN77_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[77],0.500,0.250,BWEN77_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[78],0.500,0.250,BWEN78_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[78],0.500,0.250,BWEN78_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[79],0.500,0.250,BWEN79_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[79],0.500,0.250,BWEN79_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[80],0.500,0.250,BWEN80_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[80],0.500,0.250,BWEN80_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[81],0.500,0.250,BWEN81_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[81],0.500,0.250,BWEN81_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[82],0.500,0.250,BWEN82_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[82],0.500,0.250,BWEN82_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[83],0.500,0.250,BWEN83_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[83],0.500,0.250,BWEN83_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[84],0.500,0.250,BWEN84_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[84],0.500,0.250,BWEN84_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[85],0.500,0.250,BWEN85_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[85],0.500,0.250,BWEN85_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[86],0.500,0.250,BWEN86_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[86],0.500,0.250,BWEN86_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[87],0.500,0.250,BWEN87_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[87],0.500,0.250,BWEN87_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[88],0.500,0.250,BWEN88_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[88],0.500,0.250,BWEN88_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[89],0.500,0.250,BWEN89_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[89],0.500,0.250,BWEN89_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[90],0.500,0.250,BWEN90_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[90],0.500,0.250,BWEN90_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[91],0.500,0.250,BWEN91_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[91],0.500,0.250,BWEN91_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[92],0.500,0.250,BWEN92_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[92],0.500,0.250,BWEN92_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[93],0.500,0.250,BWEN93_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[93],0.500,0.250,BWEN93_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[94],0.500,0.250,BWEN94_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[94],0.500,0.250,BWEN94_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[95],0.500,0.250,BWEN95_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[95],0.500,0.250,BWEN95_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[96],0.500,0.250,BWEN96_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[96],0.500,0.250,BWEN96_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[97],0.500,0.250,BWEN97_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[97],0.500,0.250,BWEN97_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[98],0.500,0.250,BWEN98_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[98],0.500,0.250,BWEN98_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[99],0.500,0.250,BWEN99_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[99],0.500,0.250,BWEN99_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[100],0.500,0.250,BWEN100_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[100],0.500,0.250,BWEN100_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[101],0.500,0.250,BWEN101_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[101],0.500,0.250,BWEN101_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[102],0.500,0.250,BWEN102_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[102],0.500,0.250,BWEN102_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[103],0.500,0.250,BWEN103_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[103],0.500,0.250,BWEN103_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[104],0.500,0.250,BWEN104_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[104],0.500,0.250,BWEN104_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[105],0.500,0.250,BWEN105_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[105],0.500,0.250,BWEN105_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[106],0.500,0.250,BWEN106_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[106],0.500,0.250,BWEN106_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[107],0.500,0.250,BWEN107_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[107],0.500,0.250,BWEN107_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[108],0.500,0.250,BWEN108_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[108],0.500,0.250,BWEN108_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[109],0.500,0.250,BWEN109_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[109],0.500,0.250,BWEN109_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[110],0.500,0.250,BWEN110_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[110],0.500,0.250,BWEN110_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[111],0.500,0.250,BWEN111_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[111],0.500,0.250,BWEN111_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[112],0.500,0.250,BWEN112_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[112],0.500,0.250,BWEN112_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[113],0.500,0.250,BWEN113_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[113],0.500,0.250,BWEN113_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[114],0.500,0.250,BWEN114_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[114],0.500,0.250,BWEN114_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[115],0.500,0.250,BWEN115_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[115],0.500,0.250,BWEN115_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[116],0.500,0.250,BWEN116_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[116],0.500,0.250,BWEN116_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[117],0.500,0.250,BWEN117_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[117],0.500,0.250,BWEN117_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[118],0.500,0.250,BWEN118_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[118],0.500,0.250,BWEN118_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[119],0.500,0.250,BWEN119_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[119],0.500,0.250,BWEN119_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[120],0.500,0.250,BWEN120_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[120],0.500,0.250,BWEN120_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[121],0.500,0.250,BWEN121_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[121],0.500,0.250,BWEN121_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[122],0.500,0.250,BWEN122_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[122],0.500,0.250,BWEN122_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[123],0.500,0.250,BWEN123_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[123],0.500,0.250,BWEN123_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[124],0.500,0.250,BWEN124_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[124],0.500,0.250,BWEN124_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[125],0.500,0.250,BWEN125_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[125],0.500,0.250,BWEN125_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[126],0.500,0.250,BWEN126_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[126],0.500,0.250,BWEN126_flag);
    $setuphold(posedge CLK &&& CE_flag,posedge BWEN[127],0.500,0.250,BWEN127_flag);
    $setuphold(posedge CLK &&& CE_flag,negedge BWEN[127],0.500,0.250,BWEN127_flag);
    $period(posedge CLK,1.680,CLK_CYC_flag);
    $width(posedge CLK,0.504,0,CLK_H_flag);
    $width(negedge CLK,0.504,0,CLK_L_flag);
    $setuphold(posedge CLK &&& WR0_flag,posedge D[0],0.500,0.250,D0_flag);
    $setuphold(posedge CLK &&& WR0_flag,negedge D[0],0.500,0.250,D0_flag);
    $setuphold(posedge CLK &&& WR1_flag,posedge D[1],0.500,0.250,D1_flag);
    $setuphold(posedge CLK &&& WR1_flag,negedge D[1],0.500,0.250,D1_flag);
    $setuphold(posedge CLK &&& WR2_flag,posedge D[2],0.500,0.250,D2_flag);
    $setuphold(posedge CLK &&& WR2_flag,negedge D[2],0.500,0.250,D2_flag);
    $setuphold(posedge CLK &&& WR3_flag,posedge D[3],0.500,0.250,D3_flag);
    $setuphold(posedge CLK &&& WR3_flag,negedge D[3],0.500,0.250,D3_flag);
    $setuphold(posedge CLK &&& WR4_flag,posedge D[4],0.500,0.250,D4_flag);
    $setuphold(posedge CLK &&& WR4_flag,negedge D[4],0.500,0.250,D4_flag);
    $setuphold(posedge CLK &&& WR5_flag,posedge D[5],0.500,0.250,D5_flag);
    $setuphold(posedge CLK &&& WR5_flag,negedge D[5],0.500,0.250,D5_flag);
    $setuphold(posedge CLK &&& WR6_flag,posedge D[6],0.500,0.250,D6_flag);
    $setuphold(posedge CLK &&& WR6_flag,negedge D[6],0.500,0.250,D6_flag);
    $setuphold(posedge CLK &&& WR7_flag,posedge D[7],0.500,0.250,D7_flag);
    $setuphold(posedge CLK &&& WR7_flag,negedge D[7],0.500,0.250,D7_flag);
    $setuphold(posedge CLK &&& WR8_flag,posedge D[8],0.500,0.250,D8_flag);
    $setuphold(posedge CLK &&& WR8_flag,negedge D[8],0.500,0.250,D8_flag);
    $setuphold(posedge CLK &&& WR9_flag,posedge D[9],0.500,0.250,D9_flag);
    $setuphold(posedge CLK &&& WR9_flag,negedge D[9],0.500,0.250,D9_flag);
    $setuphold(posedge CLK &&& WR10_flag,posedge D[10],0.500,0.250,D10_flag);
    $setuphold(posedge CLK &&& WR10_flag,negedge D[10],0.500,0.250,D10_flag);
    $setuphold(posedge CLK &&& WR11_flag,posedge D[11],0.500,0.250,D11_flag);
    $setuphold(posedge CLK &&& WR11_flag,negedge D[11],0.500,0.250,D11_flag);
    $setuphold(posedge CLK &&& WR12_flag,posedge D[12],0.500,0.250,D12_flag);
    $setuphold(posedge CLK &&& WR12_flag,negedge D[12],0.500,0.250,D12_flag);
    $setuphold(posedge CLK &&& WR13_flag,posedge D[13],0.500,0.250,D13_flag);
    $setuphold(posedge CLK &&& WR13_flag,negedge D[13],0.500,0.250,D13_flag);
    $setuphold(posedge CLK &&& WR14_flag,posedge D[14],0.500,0.250,D14_flag);
    $setuphold(posedge CLK &&& WR14_flag,negedge D[14],0.500,0.250,D14_flag);
    $setuphold(posedge CLK &&& WR15_flag,posedge D[15],0.500,0.250,D15_flag);
    $setuphold(posedge CLK &&& WR15_flag,negedge D[15],0.500,0.250,D15_flag);
    $setuphold(posedge CLK &&& WR16_flag,posedge D[16],0.500,0.250,D16_flag);
    $setuphold(posedge CLK &&& WR16_flag,negedge D[16],0.500,0.250,D16_flag);
    $setuphold(posedge CLK &&& WR17_flag,posedge D[17],0.500,0.250,D17_flag);
    $setuphold(posedge CLK &&& WR17_flag,negedge D[17],0.500,0.250,D17_flag);
    $setuphold(posedge CLK &&& WR18_flag,posedge D[18],0.500,0.250,D18_flag);
    $setuphold(posedge CLK &&& WR18_flag,negedge D[18],0.500,0.250,D18_flag);
    $setuphold(posedge CLK &&& WR19_flag,posedge D[19],0.500,0.250,D19_flag);
    $setuphold(posedge CLK &&& WR19_flag,negedge D[19],0.500,0.250,D19_flag);
    $setuphold(posedge CLK &&& WR20_flag,posedge D[20],0.500,0.250,D20_flag);
    $setuphold(posedge CLK &&& WR20_flag,negedge D[20],0.500,0.250,D20_flag);
    $setuphold(posedge CLK &&& WR21_flag,posedge D[21],0.500,0.250,D21_flag);
    $setuphold(posedge CLK &&& WR21_flag,negedge D[21],0.500,0.250,D21_flag);
    $setuphold(posedge CLK &&& WR22_flag,posedge D[22],0.500,0.250,D22_flag);
    $setuphold(posedge CLK &&& WR22_flag,negedge D[22],0.500,0.250,D22_flag);
    $setuphold(posedge CLK &&& WR23_flag,posedge D[23],0.500,0.250,D23_flag);
    $setuphold(posedge CLK &&& WR23_flag,negedge D[23],0.500,0.250,D23_flag);
    $setuphold(posedge CLK &&& WR24_flag,posedge D[24],0.500,0.250,D24_flag);
    $setuphold(posedge CLK &&& WR24_flag,negedge D[24],0.500,0.250,D24_flag);
    $setuphold(posedge CLK &&& WR25_flag,posedge D[25],0.500,0.250,D25_flag);
    $setuphold(posedge CLK &&& WR25_flag,negedge D[25],0.500,0.250,D25_flag);
    $setuphold(posedge CLK &&& WR26_flag,posedge D[26],0.500,0.250,D26_flag);
    $setuphold(posedge CLK &&& WR26_flag,negedge D[26],0.500,0.250,D26_flag);
    $setuphold(posedge CLK &&& WR27_flag,posedge D[27],0.500,0.250,D27_flag);
    $setuphold(posedge CLK &&& WR27_flag,negedge D[27],0.500,0.250,D27_flag);
    $setuphold(posedge CLK &&& WR28_flag,posedge D[28],0.500,0.250,D28_flag);
    $setuphold(posedge CLK &&& WR28_flag,negedge D[28],0.500,0.250,D28_flag);
    $setuphold(posedge CLK &&& WR29_flag,posedge D[29],0.500,0.250,D29_flag);
    $setuphold(posedge CLK &&& WR29_flag,negedge D[29],0.500,0.250,D29_flag);
    $setuphold(posedge CLK &&& WR30_flag,posedge D[30],0.500,0.250,D30_flag);
    $setuphold(posedge CLK &&& WR30_flag,negedge D[30],0.500,0.250,D30_flag);
    $setuphold(posedge CLK &&& WR31_flag,posedge D[31],0.500,0.250,D31_flag);
    $setuphold(posedge CLK &&& WR31_flag,negedge D[31],0.500,0.250,D31_flag);
    $setuphold(posedge CLK &&& WR32_flag,posedge D[32],0.500,0.250,D32_flag);
    $setuphold(posedge CLK &&& WR32_flag,negedge D[32],0.500,0.250,D32_flag);
    $setuphold(posedge CLK &&& WR33_flag,posedge D[33],0.500,0.250,D33_flag);
    $setuphold(posedge CLK &&& WR33_flag,negedge D[33],0.500,0.250,D33_flag);
    $setuphold(posedge CLK &&& WR34_flag,posedge D[34],0.500,0.250,D34_flag);
    $setuphold(posedge CLK &&& WR34_flag,negedge D[34],0.500,0.250,D34_flag);
    $setuphold(posedge CLK &&& WR35_flag,posedge D[35],0.500,0.250,D35_flag);
    $setuphold(posedge CLK &&& WR35_flag,negedge D[35],0.500,0.250,D35_flag);
    $setuphold(posedge CLK &&& WR36_flag,posedge D[36],0.500,0.250,D36_flag);
    $setuphold(posedge CLK &&& WR36_flag,negedge D[36],0.500,0.250,D36_flag);
    $setuphold(posedge CLK &&& WR37_flag,posedge D[37],0.500,0.250,D37_flag);
    $setuphold(posedge CLK &&& WR37_flag,negedge D[37],0.500,0.250,D37_flag);
    $setuphold(posedge CLK &&& WR38_flag,posedge D[38],0.500,0.250,D38_flag);
    $setuphold(posedge CLK &&& WR38_flag,negedge D[38],0.500,0.250,D38_flag);
    $setuphold(posedge CLK &&& WR39_flag,posedge D[39],0.500,0.250,D39_flag);
    $setuphold(posedge CLK &&& WR39_flag,negedge D[39],0.500,0.250,D39_flag);
    $setuphold(posedge CLK &&& WR40_flag,posedge D[40],0.500,0.250,D40_flag);
    $setuphold(posedge CLK &&& WR40_flag,negedge D[40],0.500,0.250,D40_flag);
    $setuphold(posedge CLK &&& WR41_flag,posedge D[41],0.500,0.250,D41_flag);
    $setuphold(posedge CLK &&& WR41_flag,negedge D[41],0.500,0.250,D41_flag);
    $setuphold(posedge CLK &&& WR42_flag,posedge D[42],0.500,0.250,D42_flag);
    $setuphold(posedge CLK &&& WR42_flag,negedge D[42],0.500,0.250,D42_flag);
    $setuphold(posedge CLK &&& WR43_flag,posedge D[43],0.500,0.250,D43_flag);
    $setuphold(posedge CLK &&& WR43_flag,negedge D[43],0.500,0.250,D43_flag);
    $setuphold(posedge CLK &&& WR44_flag,posedge D[44],0.500,0.250,D44_flag);
    $setuphold(posedge CLK &&& WR44_flag,negedge D[44],0.500,0.250,D44_flag);
    $setuphold(posedge CLK &&& WR45_flag,posedge D[45],0.500,0.250,D45_flag);
    $setuphold(posedge CLK &&& WR45_flag,negedge D[45],0.500,0.250,D45_flag);
    $setuphold(posedge CLK &&& WR46_flag,posedge D[46],0.500,0.250,D46_flag);
    $setuphold(posedge CLK &&& WR46_flag,negedge D[46],0.500,0.250,D46_flag);
    $setuphold(posedge CLK &&& WR47_flag,posedge D[47],0.500,0.250,D47_flag);
    $setuphold(posedge CLK &&& WR47_flag,negedge D[47],0.500,0.250,D47_flag);
    $setuphold(posedge CLK &&& WR48_flag,posedge D[48],0.500,0.250,D48_flag);
    $setuphold(posedge CLK &&& WR48_flag,negedge D[48],0.500,0.250,D48_flag);
    $setuphold(posedge CLK &&& WR49_flag,posedge D[49],0.500,0.250,D49_flag);
    $setuphold(posedge CLK &&& WR49_flag,negedge D[49],0.500,0.250,D49_flag);
    $setuphold(posedge CLK &&& WR50_flag,posedge D[50],0.500,0.250,D50_flag);
    $setuphold(posedge CLK &&& WR50_flag,negedge D[50],0.500,0.250,D50_flag);
    $setuphold(posedge CLK &&& WR51_flag,posedge D[51],0.500,0.250,D51_flag);
    $setuphold(posedge CLK &&& WR51_flag,negedge D[51],0.500,0.250,D51_flag);
    $setuphold(posedge CLK &&& WR52_flag,posedge D[52],0.500,0.250,D52_flag);
    $setuphold(posedge CLK &&& WR52_flag,negedge D[52],0.500,0.250,D52_flag);
    $setuphold(posedge CLK &&& WR53_flag,posedge D[53],0.500,0.250,D53_flag);
    $setuphold(posedge CLK &&& WR53_flag,negedge D[53],0.500,0.250,D53_flag);
    $setuphold(posedge CLK &&& WR54_flag,posedge D[54],0.500,0.250,D54_flag);
    $setuphold(posedge CLK &&& WR54_flag,negedge D[54],0.500,0.250,D54_flag);
    $setuphold(posedge CLK &&& WR55_flag,posedge D[55],0.500,0.250,D55_flag);
    $setuphold(posedge CLK &&& WR55_flag,negedge D[55],0.500,0.250,D55_flag);
    $setuphold(posedge CLK &&& WR56_flag,posedge D[56],0.500,0.250,D56_flag);
    $setuphold(posedge CLK &&& WR56_flag,negedge D[56],0.500,0.250,D56_flag);
    $setuphold(posedge CLK &&& WR57_flag,posedge D[57],0.500,0.250,D57_flag);
    $setuphold(posedge CLK &&& WR57_flag,negedge D[57],0.500,0.250,D57_flag);
    $setuphold(posedge CLK &&& WR58_flag,posedge D[58],0.500,0.250,D58_flag);
    $setuphold(posedge CLK &&& WR58_flag,negedge D[58],0.500,0.250,D58_flag);
    $setuphold(posedge CLK &&& WR59_flag,posedge D[59],0.500,0.250,D59_flag);
    $setuphold(posedge CLK &&& WR59_flag,negedge D[59],0.500,0.250,D59_flag);
    $setuphold(posedge CLK &&& WR60_flag,posedge D[60],0.500,0.250,D60_flag);
    $setuphold(posedge CLK &&& WR60_flag,negedge D[60],0.500,0.250,D60_flag);
    $setuphold(posedge CLK &&& WR61_flag,posedge D[61],0.500,0.250,D61_flag);
    $setuphold(posedge CLK &&& WR61_flag,negedge D[61],0.500,0.250,D61_flag);
    $setuphold(posedge CLK &&& WR62_flag,posedge D[62],0.500,0.250,D62_flag);
    $setuphold(posedge CLK &&& WR62_flag,negedge D[62],0.500,0.250,D62_flag);
    $setuphold(posedge CLK &&& WR63_flag,posedge D[63],0.500,0.250,D63_flag);
    $setuphold(posedge CLK &&& WR63_flag,negedge D[63],0.500,0.250,D63_flag);
    $setuphold(posedge CLK &&& WR64_flag,posedge D[64],0.500,0.250,D64_flag);
    $setuphold(posedge CLK &&& WR64_flag,negedge D[64],0.500,0.250,D64_flag);
    $setuphold(posedge CLK &&& WR65_flag,posedge D[65],0.500,0.250,D65_flag);
    $setuphold(posedge CLK &&& WR65_flag,negedge D[65],0.500,0.250,D65_flag);
    $setuphold(posedge CLK &&& WR66_flag,posedge D[66],0.500,0.250,D66_flag);
    $setuphold(posedge CLK &&& WR66_flag,negedge D[66],0.500,0.250,D66_flag);
    $setuphold(posedge CLK &&& WR67_flag,posedge D[67],0.500,0.250,D67_flag);
    $setuphold(posedge CLK &&& WR67_flag,negedge D[67],0.500,0.250,D67_flag);
    $setuphold(posedge CLK &&& WR68_flag,posedge D[68],0.500,0.250,D68_flag);
    $setuphold(posedge CLK &&& WR68_flag,negedge D[68],0.500,0.250,D68_flag);
    $setuphold(posedge CLK &&& WR69_flag,posedge D[69],0.500,0.250,D69_flag);
    $setuphold(posedge CLK &&& WR69_flag,negedge D[69],0.500,0.250,D69_flag);
    $setuphold(posedge CLK &&& WR70_flag,posedge D[70],0.500,0.250,D70_flag);
    $setuphold(posedge CLK &&& WR70_flag,negedge D[70],0.500,0.250,D70_flag);
    $setuphold(posedge CLK &&& WR71_flag,posedge D[71],0.500,0.250,D71_flag);
    $setuphold(posedge CLK &&& WR71_flag,negedge D[71],0.500,0.250,D71_flag);
    $setuphold(posedge CLK &&& WR72_flag,posedge D[72],0.500,0.250,D72_flag);
    $setuphold(posedge CLK &&& WR72_flag,negedge D[72],0.500,0.250,D72_flag);
    $setuphold(posedge CLK &&& WR73_flag,posedge D[73],0.500,0.250,D73_flag);
    $setuphold(posedge CLK &&& WR73_flag,negedge D[73],0.500,0.250,D73_flag);
    $setuphold(posedge CLK &&& WR74_flag,posedge D[74],0.500,0.250,D74_flag);
    $setuphold(posedge CLK &&& WR74_flag,negedge D[74],0.500,0.250,D74_flag);
    $setuphold(posedge CLK &&& WR75_flag,posedge D[75],0.500,0.250,D75_flag);
    $setuphold(posedge CLK &&& WR75_flag,negedge D[75],0.500,0.250,D75_flag);
    $setuphold(posedge CLK &&& WR76_flag,posedge D[76],0.500,0.250,D76_flag);
    $setuphold(posedge CLK &&& WR76_flag,negedge D[76],0.500,0.250,D76_flag);
    $setuphold(posedge CLK &&& WR77_flag,posedge D[77],0.500,0.250,D77_flag);
    $setuphold(posedge CLK &&& WR77_flag,negedge D[77],0.500,0.250,D77_flag);
    $setuphold(posedge CLK &&& WR78_flag,posedge D[78],0.500,0.250,D78_flag);
    $setuphold(posedge CLK &&& WR78_flag,negedge D[78],0.500,0.250,D78_flag);
    $setuphold(posedge CLK &&& WR79_flag,posedge D[79],0.500,0.250,D79_flag);
    $setuphold(posedge CLK &&& WR79_flag,negedge D[79],0.500,0.250,D79_flag);
    $setuphold(posedge CLK &&& WR80_flag,posedge D[80],0.500,0.250,D80_flag);
    $setuphold(posedge CLK &&& WR80_flag,negedge D[80],0.500,0.250,D80_flag);
    $setuphold(posedge CLK &&& WR81_flag,posedge D[81],0.500,0.250,D81_flag);
    $setuphold(posedge CLK &&& WR81_flag,negedge D[81],0.500,0.250,D81_flag);
    $setuphold(posedge CLK &&& WR82_flag,posedge D[82],0.500,0.250,D82_flag);
    $setuphold(posedge CLK &&& WR82_flag,negedge D[82],0.500,0.250,D82_flag);
    $setuphold(posedge CLK &&& WR83_flag,posedge D[83],0.500,0.250,D83_flag);
    $setuphold(posedge CLK &&& WR83_flag,negedge D[83],0.500,0.250,D83_flag);
    $setuphold(posedge CLK &&& WR84_flag,posedge D[84],0.500,0.250,D84_flag);
    $setuphold(posedge CLK &&& WR84_flag,negedge D[84],0.500,0.250,D84_flag);
    $setuphold(posedge CLK &&& WR85_flag,posedge D[85],0.500,0.250,D85_flag);
    $setuphold(posedge CLK &&& WR85_flag,negedge D[85],0.500,0.250,D85_flag);
    $setuphold(posedge CLK &&& WR86_flag,posedge D[86],0.500,0.250,D86_flag);
    $setuphold(posedge CLK &&& WR86_flag,negedge D[86],0.500,0.250,D86_flag);
    $setuphold(posedge CLK &&& WR87_flag,posedge D[87],0.500,0.250,D87_flag);
    $setuphold(posedge CLK &&& WR87_flag,negedge D[87],0.500,0.250,D87_flag);
    $setuphold(posedge CLK &&& WR88_flag,posedge D[88],0.500,0.250,D88_flag);
    $setuphold(posedge CLK &&& WR88_flag,negedge D[88],0.500,0.250,D88_flag);
    $setuphold(posedge CLK &&& WR89_flag,posedge D[89],0.500,0.250,D89_flag);
    $setuphold(posedge CLK &&& WR89_flag,negedge D[89],0.500,0.250,D89_flag);
    $setuphold(posedge CLK &&& WR90_flag,posedge D[90],0.500,0.250,D90_flag);
    $setuphold(posedge CLK &&& WR90_flag,negedge D[90],0.500,0.250,D90_flag);
    $setuphold(posedge CLK &&& WR91_flag,posedge D[91],0.500,0.250,D91_flag);
    $setuphold(posedge CLK &&& WR91_flag,negedge D[91],0.500,0.250,D91_flag);
    $setuphold(posedge CLK &&& WR92_flag,posedge D[92],0.500,0.250,D92_flag);
    $setuphold(posedge CLK &&& WR92_flag,negedge D[92],0.500,0.250,D92_flag);
    $setuphold(posedge CLK &&& WR93_flag,posedge D[93],0.500,0.250,D93_flag);
    $setuphold(posedge CLK &&& WR93_flag,negedge D[93],0.500,0.250,D93_flag);
    $setuphold(posedge CLK &&& WR94_flag,posedge D[94],0.500,0.250,D94_flag);
    $setuphold(posedge CLK &&& WR94_flag,negedge D[94],0.500,0.250,D94_flag);
    $setuphold(posedge CLK &&& WR95_flag,posedge D[95],0.500,0.250,D95_flag);
    $setuphold(posedge CLK &&& WR95_flag,negedge D[95],0.500,0.250,D95_flag);
    $setuphold(posedge CLK &&& WR96_flag,posedge D[96],0.500,0.250,D96_flag);
    $setuphold(posedge CLK &&& WR96_flag,negedge D[96],0.500,0.250,D96_flag);
    $setuphold(posedge CLK &&& WR97_flag,posedge D[97],0.500,0.250,D97_flag);
    $setuphold(posedge CLK &&& WR97_flag,negedge D[97],0.500,0.250,D97_flag);
    $setuphold(posedge CLK &&& WR98_flag,posedge D[98],0.500,0.250,D98_flag);
    $setuphold(posedge CLK &&& WR98_flag,negedge D[98],0.500,0.250,D98_flag);
    $setuphold(posedge CLK &&& WR99_flag,posedge D[99],0.500,0.250,D99_flag);
    $setuphold(posedge CLK &&& WR99_flag,negedge D[99],0.500,0.250,D99_flag);
    $setuphold(posedge CLK &&& WR100_flag,posedge D[100],0.500,0.250,D100_flag);
    $setuphold(posedge CLK &&& WR100_flag,negedge D[100],0.500,0.250,D100_flag);
    $setuphold(posedge CLK &&& WR101_flag,posedge D[101],0.500,0.250,D101_flag);
    $setuphold(posedge CLK &&& WR101_flag,negedge D[101],0.500,0.250,D101_flag);
    $setuphold(posedge CLK &&& WR102_flag,posedge D[102],0.500,0.250,D102_flag);
    $setuphold(posedge CLK &&& WR102_flag,negedge D[102],0.500,0.250,D102_flag);
    $setuphold(posedge CLK &&& WR103_flag,posedge D[103],0.500,0.250,D103_flag);
    $setuphold(posedge CLK &&& WR103_flag,negedge D[103],0.500,0.250,D103_flag);
    $setuphold(posedge CLK &&& WR104_flag,posedge D[104],0.500,0.250,D104_flag);
    $setuphold(posedge CLK &&& WR104_flag,negedge D[104],0.500,0.250,D104_flag);
    $setuphold(posedge CLK &&& WR105_flag,posedge D[105],0.500,0.250,D105_flag);
    $setuphold(posedge CLK &&& WR105_flag,negedge D[105],0.500,0.250,D105_flag);
    $setuphold(posedge CLK &&& WR106_flag,posedge D[106],0.500,0.250,D106_flag);
    $setuphold(posedge CLK &&& WR106_flag,negedge D[106],0.500,0.250,D106_flag);
    $setuphold(posedge CLK &&& WR107_flag,posedge D[107],0.500,0.250,D107_flag);
    $setuphold(posedge CLK &&& WR107_flag,negedge D[107],0.500,0.250,D107_flag);
    $setuphold(posedge CLK &&& WR108_flag,posedge D[108],0.500,0.250,D108_flag);
    $setuphold(posedge CLK &&& WR108_flag,negedge D[108],0.500,0.250,D108_flag);
    $setuphold(posedge CLK &&& WR109_flag,posedge D[109],0.500,0.250,D109_flag);
    $setuphold(posedge CLK &&& WR109_flag,negedge D[109],0.500,0.250,D109_flag);
    $setuphold(posedge CLK &&& WR110_flag,posedge D[110],0.500,0.250,D110_flag);
    $setuphold(posedge CLK &&& WR110_flag,negedge D[110],0.500,0.250,D110_flag);
    $setuphold(posedge CLK &&& WR111_flag,posedge D[111],0.500,0.250,D111_flag);
    $setuphold(posedge CLK &&& WR111_flag,negedge D[111],0.500,0.250,D111_flag);
    $setuphold(posedge CLK &&& WR112_flag,posedge D[112],0.500,0.250,D112_flag);
    $setuphold(posedge CLK &&& WR112_flag,negedge D[112],0.500,0.250,D112_flag);
    $setuphold(posedge CLK &&& WR113_flag,posedge D[113],0.500,0.250,D113_flag);
    $setuphold(posedge CLK &&& WR113_flag,negedge D[113],0.500,0.250,D113_flag);
    $setuphold(posedge CLK &&& WR114_flag,posedge D[114],0.500,0.250,D114_flag);
    $setuphold(posedge CLK &&& WR114_flag,negedge D[114],0.500,0.250,D114_flag);
    $setuphold(posedge CLK &&& WR115_flag,posedge D[115],0.500,0.250,D115_flag);
    $setuphold(posedge CLK &&& WR115_flag,negedge D[115],0.500,0.250,D115_flag);
    $setuphold(posedge CLK &&& WR116_flag,posedge D[116],0.500,0.250,D116_flag);
    $setuphold(posedge CLK &&& WR116_flag,negedge D[116],0.500,0.250,D116_flag);
    $setuphold(posedge CLK &&& WR117_flag,posedge D[117],0.500,0.250,D117_flag);
    $setuphold(posedge CLK &&& WR117_flag,negedge D[117],0.500,0.250,D117_flag);
    $setuphold(posedge CLK &&& WR118_flag,posedge D[118],0.500,0.250,D118_flag);
    $setuphold(posedge CLK &&& WR118_flag,negedge D[118],0.500,0.250,D118_flag);
    $setuphold(posedge CLK &&& WR119_flag,posedge D[119],0.500,0.250,D119_flag);
    $setuphold(posedge CLK &&& WR119_flag,negedge D[119],0.500,0.250,D119_flag);
    $setuphold(posedge CLK &&& WR120_flag,posedge D[120],0.500,0.250,D120_flag);
    $setuphold(posedge CLK &&& WR120_flag,negedge D[120],0.500,0.250,D120_flag);
    $setuphold(posedge CLK &&& WR121_flag,posedge D[121],0.500,0.250,D121_flag);
    $setuphold(posedge CLK &&& WR121_flag,negedge D[121],0.500,0.250,D121_flag);
    $setuphold(posedge CLK &&& WR122_flag,posedge D[122],0.500,0.250,D122_flag);
    $setuphold(posedge CLK &&& WR122_flag,negedge D[122],0.500,0.250,D122_flag);
    $setuphold(posedge CLK &&& WR123_flag,posedge D[123],0.500,0.250,D123_flag);
    $setuphold(posedge CLK &&& WR123_flag,negedge D[123],0.500,0.250,D123_flag);
    $setuphold(posedge CLK &&& WR124_flag,posedge D[124],0.500,0.250,D124_flag);
    $setuphold(posedge CLK &&& WR124_flag,negedge D[124],0.500,0.250,D124_flag);
    $setuphold(posedge CLK &&& WR125_flag,posedge D[125],0.500,0.250,D125_flag);
    $setuphold(posedge CLK &&& WR125_flag,negedge D[125],0.500,0.250,D125_flag);
    $setuphold(posedge CLK &&& WR126_flag,posedge D[126],0.500,0.250,D126_flag);
    $setuphold(posedge CLK &&& WR126_flag,negedge D[126],0.500,0.250,D126_flag);
    $setuphold(posedge CLK &&& WR127_flag,posedge D[127],0.500,0.250,D127_flag);
    $setuphold(posedge CLK &&& WR127_flag,negedge D[127],0.500,0.250,D127_flag);
  endspecify

endmodule

`endcelldefine


